Many portable products, such as cell phones, laptop computers, personal digital assistants (PDAs) or the like, require the use of a processor executing a program supporting communication and multimedia applications. The processing system for such products includes one or more processors, each with storage for instructions, input operands, and results of execution. For example, the instructions, input operands, and results of execution for a processor may be stored in a hierarchical memory subsystem consisting of a general purpose register file, multi-level instruction caches, data caches, and a system memory.
In order to provide high code density, a native instruction set architecture (ISA) may be used having two instruction formats, such as a 16-bit instruction format that is a subset of a 32-bit instruction format. In many cases, a fetched 16-bit instruction is transformed by a processor into a 32-bit instruction prior to or in a decoding process which allows the execution hardware to be designed to only support the 32-bit instruction format. The use of 16-bit instructions that are a subset of 32-bit instructions is a restriction that limits the amount of information that can be encoded into a 16-bit format. For example, a 16-bit instruction format may limit the number of addressable source operand registers and destination registers that may be specified. A 16-bit instruction format, for example, may use 3-bit or 4-bit register file address fields, while a 32-bit instruction may use 5-bit fields. Processor pipeline complexity may also increase if the two formats are intermixed in a program due in part to instruction addressing restrictions, such as, branching to 16-bit and 32-bit instructions. Also, requirements for code compression vary from program to program making a fixed 16-bit instruction format chosen for one program less advantageous for use by a different program. In this regard, legacy code for existing processors may not be able to effectively utilize the two instruction formats to significantly improve code density and meet real time requirements. These and other restrictions limit the effectiveness of reduced size instructions having fields that are subsets of fields used in the standard size instructions.